Semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. Integrated circuits (IC) fabrication technologies have been exploited to a limit and need more interactions between manufacturing and designing.
One such limit relates to metal thickness. Current IC design flow only considers ideal or simplified models for metal thickness substitution. The current method for signal analysis and design performance evaluation cannot reflect the variations in metal thickness that actually occur during fabrication. For example, in the current design flow, the IC design layouts have no proper way to connect to and incorporate with a chemical mechanical polishing (CMP) process. However, the variations of the metal thickness from the CMP process seriously impacts the signal wire characteristics, IC design functionality, and performance. For various environments, the same metal wire may have different thicknesses due to the CMP process, which results in variations of electrical properties of the signal wire.